LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;

entity contador2std_logic is    
port(
	rst : in std_logic;
	ck: in std_logic;
	e: in std_logic;
	q0 : out std_logic;
	q1 : out std_logic);
end;

architecture mix of contador2std_logic is
	signal d0,d1,q0_s,q1_s : std_logic;
	
	component ffd
	port(
    clr: in std_logic;
    ck: in std_logic;
    d: in std_logic;
    e:in std_logic;
    q: out std_logic;
    nq: out std_logic 
    );
	end component;
begin
	ffd0: ffd port map ( rst,ck,d0,e,q0_s,open);
	ffd1: ffd port map ( rst,ck,d1,e,q1_s,open);
	d0 <= not q0_s ;
	d1 <= q0_s xor q1_s ;
	 q1 <= q1_s;
	 q0 <= q0_s;
	
end ;


